1. Field of the Invention
The present invention relates to a chip, a chip stack, and a method of manufacturing the same, and more particularly, to a chip, a chip stack, and a method of manufacturing the same in which a chip manufacturing process is simplified, chip performance is improved, and a footprint for a chip stack is made small by forming a metal layer protruding from the bottom of a wafer up to a predetermined thickness in a via hole penetrating the wafer to expose the bottom of a pad formed on the wafer.
2. Discussion of Related Art
The ongoing development of wireless communication and digital multimedia technology, coupled with increasing consumer demand, continues to fuel the trend toward miniaturization, high performance, high integration, and multi-functionality of portable digital electronic devices such as portable phones, personal digital assistants (PDA), and high performance multimedia devices.
For miniaturization of such portable digital electronic devices, system on chip (SoC) technology, in which integrated circuits (ICs) having different functions are integrated into one chip to function as a system, has been extensively researched.
However, SoC technology can only integrate ICs manufactured by the same processes into one chip. For example, SoC technology cannot be applied to a metal oxide semiconductor, a bipolar semiconductor, and a RF chip because these IC's are fabricated on different wafers.
As an alternative to SoC, research into system on package (SoP) technology is currently progressing. SoP integrates ICs not integrated into one chip by SoC. In order to implement SoP technology, a method of stacking ICs to be mounted has been suggested as a way to reduce a footprint of the ICs.
Such a chip stack is classified into a package stack and a bare chip stack. The bare chip stack has a relatively small footprint and the advantage of small size compared to the package stack.
Many chip stacking methods have been suggested to date. The package stack has the disadvantage of involving a bulky process using wire bonding or a chip carrier. This results in large inductance which degrades the performance of ICs. Thus, the chip stack better facilitates miniaturization.
PCT/US1999/09744, entitled “Chip Stack and Method of Making the same” discloses a conventional chip stack technique using a carrier. The method involves stacking chips by putting a chip on a chip carrier and forming a bump on the carrier. However, conventional art using the chip carrier has the problem of a large footprint.
U.S. Pat. No. 6,395,630, entitled “Stacked Integrated Circuits” discloses a chip stack technique in which a bump is formed in the chip such that a hole having an aspect ratio of 100 to 200 is formed to penetrate a wafer and a coaxial conductor is formed in the hole using a chemical vapor deposition (CVD) technique.
However, the conventional art in which the bump is formed in the chip has several problems. These are, it is difficult to form a hole having a high aspect ratio, a process for forming the coaxial conductor in the hole using the CVD technique has a low deposition rate (e.g., 100 Å/min) and requires a long processing time, and an inner conductor process and an outer conductor process should be performed separately.